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101

XMEGA A [MANUAL]

8077I–AVR–11/2012

8.4

Power Reduction Registers

The power reduction (PR) registers provide a method to stop the clock to individual peripherals. When this is done, the

current state of the peripheral is frozen and the associated I/O registers cannot be read or written. Resources used by the

peripheral will remain occupied; hence, the peripheral should be disabled before stopping the clock. Enabling the clock to

a peripheral again puts the peripheral in the same state as before it was stopped. This can be used in idle mode and

active modes to reduce the overall power consumption. In all other sleep modes, the peripheral clock is already stopped.

Not all devices have all the peripherals associated with a bit in the power reduction registers. Setting a power reduction

bit for a peripheral that is not available will have no effect.

8.5

Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an AVR MCU controlled

system. In general, correct sleep modes should be selected and used to ensure that only the modules required for the

application are operating.

All unneeded functions should be disabled. In particular, the following modules may need special consideration when

trying to achieve the lowest possible power consumption.

8.5.1

Analog-to-Digital Converter - ADC

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any

sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to

“ADC – Analog-to-Digital Converter” on page 283 for details on ADC operation.

8.5.2

Analog Comparator - AC

When entering idle mode, the analog comparator should be disabled if not used. In other sleep modes, the analog

comparator is automatically disabled. However, if the analog comparator is set up to use the internal voltage reference as

input, the analog comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be

enabled, irrespective of sleep mode. Refer to “AC – Analog Comparator” on page 322 for details on how to configure the

analog comparator.

8.5.3

Brownout Detector

If the brownout detector is not needed by the application, this module should be turned off. If the brownout detector is

enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and always consume power. In the deeper sleep

modes, it can be turned off and set in sampled mode to reduce current consumption. Refer to “Brownout Detection” on

page 108 for details on how to configure the brownout detector.

8.5.4

Watchdog Timer

If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled,

it will be enabled in all sleep modes and, hence, always consume power. Refer to “WDT – Watchdog Timer” on page 120

for details on how to configure the watchdog timer.

8.5.5

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. Most important is to ensure that

no pins drive resistive loads. In sleep modes where the Peripheral Clock (ClkPER) is stopped, the input buffers of the

device will be disabled. This ensures that no power is consumed by the input logic when not needed.

8.5.6

On-chip Debug System

If the On-chip debug system is enabled and the chip enters sleep mode, the main clock source is enabled and hence

always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

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